* Digitronix (updated 2024-11-28) ~ youtor.org

Digitronix (updated 2024-11-28)

DigiTronix CAR Bike Battery ChargerLead Acid Battery 12V Charger with Digital Voltage Display [upl. by Gearard]

DigiTronix CAR Bike Battery ChargerLead Acid Battery 12V Charger with Digital Voltage Display

Duration: 2:30
3.6K views | 9 Apr 2022

Unboxing ZedBoard FPGA amp Features Introduction Session by Digitronix Nepal [upl. by Haakon]

Unboxing ZedBoard FPGA amp Features Introduction Session by Digitronix Nepal

Duration: 3:22
10K views | 19 Jan 2017

Zynq TRD ported to Zedboard Sobel Filter Implementation with VIVADO HLS by Digitronix Nepal [upl. by Orpah179]

Zynq TRD ported to Zedboard Sobel Filter Implementation with VIVADO HLS by Digitronix Nepal

Duration: 6:39
599 views | 11 Dec 2017

DJetronic Fuel Economy [upl. by Drews724]

DJetronic Fuel Economy

Duration: 3:52
3.2K views | 10 Apr 2018

Design and Simulation of ALU on ModelSim [upl. by Sdlonyer198]

Design and Simulation of ALU on ModelSim

Duration: 9:12
4.2K views | 20 Apr 2018

How to write 12Ghs Keccak algorithm on VHDL targeting VCU1525 [upl. by Hoag]

How to write 12Ghs Keccak algorithm on VHDL targeting VCU1525

Duration: 30:20
1.7K views | 25 Feb 2019

Nexys 4 DDR FPGA based ALU design with Seven Segment [upl. by Adnaluy]

Nexys 4 DDR FPGA based ALU design with Seven Segment

Duration: 2:55
1.7K views | 23 Jan 2019

Webinar Series on FPGA Computer Vision amp Machine Learning with FPGA Feb 17 2019 [upl. by Kensell]

Webinar Series on FPGA Computer Vision amp Machine Learning with FPGA Feb 17 2019

Duration: 50:35
950 views | 18 Feb 2019

Advance Verilog Design Overview Data Types Syntax and Semantics [upl. by Salena]

Advance Verilog Design Overview Data Types Syntax and Semantics

Duration: 22:06
409 views | 3 Mar 2019

Ultra96 FPGA First Boot Up amp GPIO Control [upl. by Ahseet]

Ultra96 FPGA First Boot Up amp GPIO Control

Duration: 5:26
2.8K views | 19 Dec 2018

Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK [upl. by Fita544]

Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK

Duration: 3:07
2.3K views | 20 Jan 2017

Vending Machine Design amp Implemented on Spartan 3E Nexys 2FPGA [upl. by Curr923]

Vending Machine Design amp Implemented on Spartan 3E Nexys 2FPGA

Duration: 3:57
767 views | 8 Jul 2016

Numato Mimas V2 Building Github Project of VGA amp Seven Segment [upl. by Phipps95]

Numato Mimas V2 Building Github Project of VGA amp Seven Segment

Duration: 10:41
1.8K views | 20 Apr 2019

MATLAB based OFDM Receiver Design and Simulation Session [upl. by Ulberto]

MATLAB based OFDM Receiver Design and Simulation Session

Duration: 14:01
5.8K views | 22 Feb 2019

Verilog vs System Verilog [upl. by Jephthah]

Verilog vs System Verilog

Duration: 9:19
2.7K views | 14 Jan 2019

Zedboard Audio Processing Demo by Digitronix Nepals 8th tutorial on Zedboard [upl. by Mcconaghy]

Zedboard Audio Processing Demo by Digitronix Nepals 8th tutorial on Zedboard

Duration: 17:12
1.8K views | 5 Mar 2017

PYNQ FPGA 3rd SessionSimple Neural Net Implementation on Python by Digitronix Nepal [upl. by Yetah]

PYNQ FPGA 3rd SessionSimple Neural Net Implementation on Python by Digitronix Nepal

Duration: 21:14
9.3K views | 25 Dec 2016

Basic Image Processing in Python with Pynq FPGA amp USB Webcam [upl. by Allin]

Basic Image Processing in Python with Pynq FPGA amp USB Webcam

Duration: 6:15
11.4K views | 31 Jan 2017

Partial Reconfiguration with Xilinx VIVADO toolAn Example Design [upl. by Bauske465]

Partial Reconfiguration with Xilinx VIVADO toolAn Example Design

Duration: 9:12
3.5K views | 22 Jul 2019

Conditional Statements in Verilog always block Ifelse amp case statement [upl. by Anirehtac]

Conditional Statements in Verilog always block Ifelse amp case statement

Duration: 25:54
2.3K views | 18 Feb 2019

Hello World OpenCL acceleration on Xilinx Alveo with Nimbix Cloud [upl. by Trip]

Hello World OpenCL acceleration on Xilinx Alveo with Nimbix Cloud

Duration: 27:42
2K views | 7 Mar 2019

Ultra 96 FPGA Unboxing Session Digitronix Nepal [upl. by Aratnahs]

Ultra 96 FPGA Unboxing Session Digitronix Nepal

Duration: 3:57
2.9K views | 14 Dec 2018

Getting Started with Pynq FPGA Second Session on PynqPython Programming by Digitronix Nepal [upl. by Fair58]

Getting Started with Pynq FPGA Second Session on PynqPython Programming by Digitronix Nepal

Duration: 4:05
4.4K views | 23 Dec 2016

PCIe Development with FPGA Section 5 Lab51 loading ILA data and analyzing the PCIe Packets [upl. by Akcebar]

PCIe Development with FPGA Section 5 Lab51 loading ILA data and analyzing the PCIe Packets

Duration: 6:37
726 views | 20 Jul 2018

Mimas V2 Basic Logic Gate Design in VHDL amp Implementation with Xilinx ISE tool [upl. by Acir]

Mimas V2 Basic Logic Gate Design in VHDL amp Implementation with Xilinx ISE tool

Duration: 6:51
1.2K views | 20 Apr 2019

Machine Learning on Nimbix Cloud with VCU1525 and Alveo [upl. by Keraj]

Machine Learning on Nimbix Cloud with VCU1525 and Alveo

Duration: 19:06
444 views | 9 Mar 2019

Conditional Statements in VHDL Learn VHDL Programming with FPGA [upl. by Kowalski]

Conditional Statements in VHDL Learn VHDL Programming with FPGA

Duration: 16:23
565 views | 29 Jan 2019

Getting Started with ZedBoard with Linux Bootup and Led Blinking by Digitronix Nepal [upl. by Zoubek]

Getting Started with ZedBoard with Linux Bootup and Led Blinking by Digitronix Nepal

Duration: 5:53
13.9K views | 19 Jan 2017

Advance Verilog Design from Lexical Conventions Data Flow Modeling to Behavioral Modeling [upl. by Laucsap571]

Advance Verilog Design from Lexical Conventions Data Flow Modeling to Behavioral Modeling

Duration: 44:20
808 views | 6 Mar 2019

Numato Mimas V2 Basic Logic Gate OR Design amp Implementation with Xilinx ISE tool [upl. by Aiela353]

Numato Mimas V2 Basic Logic Gate OR Design amp Implementation with Xilinx ISE tool

Duration: 6:44
1.4K views | 20 Apr 2019

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